1. Field of the Invention
The present invention relates to a BiCMOS logic circuit comprising bipolar transistors and MOS field-effect transistors.
2. Description of the Related Art
A BiCMOS logic circuit has both the advantage inherent in a CMOS circuit, i.e., low power consumption, and that of bipolar transistors, i.e., high load-driving ability. A conventional BiCMOS disclosed in Published Unexamined Japanese Patent Application 3-34720 will be described with reference to FIG. 1.
As shown in FIG. 1, an input terminal IN is connected to the gate of a P-channel MOS FET P1 and those of N-channel MOS FETs N1 and N2. The drain of the P-channel MOS FET P1 and that of the N-channel MOS FET N2 are connected to each other, whereby the MOS FETs P1 and N2 constitute a CMOS inverter 11. The output of the inverter 11 is coupled to the base of an NPN transistor Q1. The collector and emitter of the NPN transistor Q1 are connected to the power supply V.sub.CC and an output terminal OUT, respectively.
The N-channel MOS FET N1 has its drain connected the output terminal OUT, and its source connected to the drain of an N-channel MOS FET N3. The N-channel MOS FET N3 has its gate connected to the output node of the inverter 11, and its source coupled to the ground power supply GND. The node where the source of the N-channel MOS FET N1 and the drain of the N-channel MOS FET N3 are coupled together is connected to the base of an NPN transistor Q2. The collector and emitter of the NPN transistor Q2 are connected to the output terminal OUT and the ground power supply GND, respectively.
The BiCMOS logic circuit of FIG. 1, which functions as an inverter gate, operates in the following way.
When the signal input to the terminal IN rises from the low (L) level to the high (H) level, the N-channel MOS FET N1, which is a driving transistor, is turned on, whereby base current flows in the NPN transistor Q2. As a result, the collector current of the transistor Q2 is multiplied by .beta., i.e., the emitter-ground amplification factor. The potential at the output terminal OUT is thereby pulled down to the L level. Since the P-channel MOS FET P1, which is also a driving transistor, is cut off at this time, the NPN transistor Q1, which serves as a pull-up transistor, is off.
When the signal input to the terminal IN falls from the H level to the L level, the P-channel MOS FET P1 (i.e., driving transistor) is turned on, whereas the N-channel MOS FET N2 is turned off. The NPN transistor Q1 and the N-channel MOS FET N3 are thereby turned on. Simultaneously, the N-channel MOS FET N1 (i.e., driving transistor) is turned off, whereby the NPN transistor Q2 is turned off. As a result, the potential at the output terminal OUT is pulled up to the H level.
The BiCMOS logic circuit has a problem with its pull-down side, however. The problem results from the fact that the source of the N-channel MOS FET N1 serving as a driving transistor is connected to the base of the NPN transistor Q2 which functions as a pull-down element. To be more specific, when the NPN transistor Q2 perform a pull-down operation, its base potential, i.e., the source potential of the N-channel MOS FET N1, shifts from the ground potential by the base-emitter voltage (V.sub.BE). The gate-source voltage and drain-source voltage of the N-channel MOS FET N1 inevitably decrease by V.sub.BE of the NPN transistor Q2. Consequently, the N-channel MOS FET N1 has its driving ability reduced considerably. The drain current of the N-channel MOS FET N1, i.e., the base current of the NPN transistor Q2, can no longer assume a sufficiently great value, lengthening the delay time of pull-down operation of the NPN transistor Q2. Hence, the BiCMOS logic circuit of FIG. 1 cannot operate correctly, particularly when its power-supply voltage is relatively low.
As has been described, the conventional BiCMOS logic circuit (FIG. 1) is of such a structure that the MOS FET for driving the pull-down bipolar transistor inevitably has an insufficient driving ability. The delay time in the pull-down operation of the bipolar transistor is inevitably long, and the BiCMOS logic circuit can hardly operate correctly at a low power supply voltage.